1. Field of the Invention
The invention relates to wiring method, program, and apparatus in a layout design of an LSI and, more particularly, to wiring method, program, and apparatus which take crosstalks and a wiring delay into consideration.
2. Description of the Related Arts
In recent years, with respect to an LSI designing system, an influence of a wiring delay is larger than that of a gate delay due to micro miniaturization of a transistor size. An adjacent load capacity can be mentioned as one of causes of the wiring delay. An influence of noises caused by crosstalks is also large and the adjacent load capacity can be also mentioned as one of causes of the noises. Therefore, a wiring technique to reduce the adjacent load capacity at the time of automatic wiring is demanded. In the conventional automatic wiring, when a certain net is automatically wired on the basis of a net list, a minimum adjacent spacing condition which does not become a wiring violation is given and the wiring is performed. Even if a load condition to reduce the adjacent load capacity is given, it is given to all nets and the nets are automatically wired.
Refer to JP-A-5-181936, JP-A-6-124321, JP-A-5-160375, JP-A-5-243383, JP-A-9-147009, JP-A-10-189746, and JP-A-2003-303217.
However, if the minimum adjacent spacing condition which does not become the wiring violation is given and the wiring is performed in the conventional automatic wiring as mentioned above, the adjacent load capacity is added with respect to an important path and the problems of the increase in wiring delay and the increase in crosstalk noises are caused. Even if the automatic wiring is executed by using the load condition for the adjacent capacity, since it is executed for all of the nets as targets, such a problem that the apparatus enters the state where it is difficult to complete the wiring due to a lack of channels in terms of a relation with an integration degree.